The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having fuse patterns and a fuse window cooperating therewith such that the fuse patterns are selectively blown by irradiating a laser beam through the fuse window.
With the advancement in the art of device miniaturization, the effect of defective device elements in a semiconductor integrated circuit on the overall production yield of the integrated circuit is increasing. This problem is particularly serious in large-capacity LSI memory devices of very large total number of bits such as 64 Mbit DRAMs (dynamic random access memories). Because of this problem, such large capacity LSI memory devices generally use a redundant construction in which a plurality of redundant memory cell rows or a plurality of redundant memory cell columns are provided in a memory cell array. Further, such a redundant construction generally includes a fuse typically formed of polysilicon. Thus, when a memory cell row or memory cell column containing a defective bit is to be replaced with a redundant memory cell row or a redundant memory cell column, or when to conduct other desired functional selection, it has been practiced to selectively blow a suitable fuse pattern by a laser beam or by an electrical current.
It should be noted that such a fuse pattern is generally surrounded by various semiconductor circuit elements and interconnection layers. In recent highly integrated semiconductor devices, the interconnection layer extends to the region in the vicinity of the fuse pattern, and because of this, there tends to arise the problem of poor planarization in the protective film covering the interconnection patterns in the interconnection layer when the width or pitch of the interconnection layer is reduced. When the planarization of the protective film is thus deteriorated, the step coverage of the interconnection patterns by the protective film is deteriorated, leading to void formation. Such a formation of void in the protective film causes the problem of poor resistance of the integrated circuit against moisture. Thus, in order to improve the resistance against moisture, various efforts are being made to improve the planarization of the protective film by using various protective films.
In the case when a highly planarized protective film is formed to cover the fuse, on the other hand, there inevitably arises the problem of local variation in the thickness of the protective film due to the step caused by the existence of the fuse pattern. In other words, it is difficult to cover the fuse patterns by the protective film with a uniform thickness. Further in view of the recent tendency of increase in the diameter of the semiconductor wafer, the change in the thickness of the protective film over the wafer surface is increasing. Thereby, the thickness of the protective film may change in the semiconductor chips even when the semiconductor chips are obtained from a single wafer. Further, there may be a variation in the thickness of the protective film for the different fuse patterns formed in a single semiconductor chip.
FIGS. 1A-1C show a conventional process of forming a fuse window.
Referring to FIG. 1A, a p-type Si substrate 41 is covered by an oxide film 42 and a plurality of fuse patterns 43 are formed by a patterning process of a polysilicon layer. After the formation of the fuse patterns 43, an SiO2 film 44 is deposited thereon by a CVD process so as to cover the fuse patterns 43, and an Al alloy film is deposited on the SiO2 film 44 by a PVD (physical vapor deposition) process such as a sputtering process or an evaporation deposition process. By patterning the Al alloy film thus deposited, an interconnection pattern 45 and a bonding pad 46 are formed. Next, the SiO2 film 44 is covered by another SiO2 film 47 deposited by a PCVD (plasma CVD) process so as to cover the interconnection pattern 45 and the bonding pad 46, and an SOG film is formed on the SiO2 film 47 by a spin coating process. After a heat treatment process and an etch-back process conducted by an RIE (reactive ion etching) process on the SOG film thus deposited, there is obtained a planarized structure in which the depressed part is filled with an SOG film 48. The SOG film 48 remains also adjacent to the stepped part. Further, a protective film 49 of SiN is deposited on the planarized structure by a PCVD process.
Next, in the step of FIG. 1B, a fuse window 51 and a bonding opening 52 exposing the bonding pad 46 are formed simultaneously in the SiN film 49 by an RIE process while using a resist pattern 50 as a mask, wherein the duration of the etching process is controlled such that an SiO2 film 44 remains on the fuse patterns 43.
Next, in the step of FIG. 1C, the resist pattern 50 is removed and a predetermined electrical interconnection is made at the foregoing bonding opening 52, and a laser irradiation process is conducted subsequently in which a laser beam is applied to a selected fuse pattern 43 corresponding to the necessary redundant circuit via the fuse window 51 such that the selected fuse pattern 43 is blown by the laser beam. The fuse pattern 43 may also be the one that selects a desired circuit function.
In the foregoing conventional process, it should be noted that the thickness of the insulation film remaining on the fuse patterns 43 may change variously due to the local variation in the thickness of the insulation film 44 covering the fuse patterns 43, wherein it should be noted that the foregoing local variation is caused as a result of the foregoing planarization process. When such a variation occurs in the thickness of the insulation film 44 covering various fuse patterns 43, there arises a problem in that some fuse pattern 43 is easily blown up by the laser beam irradiation while some are not. Thereby, it becomes difficult to blow the selected fuse pattern by the laser beam with reliability.
FIGS. 2A-2D show another conventional process of forming a fuse window in which a uniform thickness is guaranteed for the insulation film covering the fuse patterns 43. In FIGS. 2A-2D, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIG. 2A, the fuse patterns 43 of polysilicon are formed on the oxide film 42 covering the p-type Si substrate 41 similarly as in the case of FIG. 1A, and the fuse patterns 43 are covered by the SiO2 film 44 deposited by a CVD process. Further, an Al alloy film is deposited on the SiO2 film 44 by a sputtering process or an evaporation deposition process, followed by a patterning process to form the interconnection pattern 45 and the bonding pad 46, similarly as before. The interconnection pattern 45 and the bonding pad 46 are then covered by the SiO2 film 47 deposited by a PCVD process, and an SOG film is formed on the SiO2 film 47 by a spin coating process. Next, the SOG film thus deposited is subjected to a curing process, followed by an etch-back process conducted by an RIE process, to form a planarized structure in which the SOG film 48 fills the depressions or steps. Further, the SiN film 49 is deposited on the planarized structure thus obtained by a PCVD process as a protective film.
Next, in the step of FIG. 2B, the fuse window 51 and the bonding opening 52 are formed simultaneously by an RIE process while using the resist pattern 50 as a mask, wherein the fuse window 51 is formed such that the SiO2 film 44 is removed entirely from the fuse window 51.
In FIG. 2B, it may seem that the exposed surface of the oxide film 42 is entirely flat. In the actual structure, the oxide film 42 experiences an etching action, and because of this, the surface of the exposed oxide film 42 tends to show slight projection or depression reflecting the thickness variation of the insulation film on the fuse pattern 43.
Next, in the step of FIG. 2C, the resist pattern 50 is removed and an SiO2 film 53 is deposited on the entire structure thus obtained by a CVD process to form a cover film of the fuse patterns 43. In this process, the projections and depressions formed in the oxide film 42 as a result of the previous etching process are filled by the SiO2 film 53.
Next, in the step of FIG. 2D, the SiO2 film 53 covering the surface of the bonding opening 52 is selectively removed by conducting an RIE process while using a new resist pattern 54 as a mask, to expose the bonding pad 46. Next, the resist pattern 54 is removed and the electrical interconnection is made at the bonding opening 52. Further, a laser beam is irradiated to a selected fuse pattern 43 corresponding to the desired redundant circuit via the fuse window 51 to blow the same. Similarly as before, the fuse pattern 43 may be the one that selects a desired circuit function.
In this prior art process, it is possible to form the SiO2 film 53 to have a uniform thickness to some degree, by controlling the condition of deposition. Thereby, it is possible to obtain a generally uniform laser blowing property for each of the fuse patterns or for each of the semiconductor chips.
FIGS. 3A-3C show a further conventional process of forming fuse patterns that uses an etching stopper.
Referring to FIG. 3A, a Si substrate 61 is selectively oxidized to form a field insulation film 62 on the surface of the substrate 61, and an SiO2 capacitor insulation film 63 is formed on the exposed surface of the Si substrate 61 with a thickness of 100 nm. Next, the structure thus obtained is covered with a polysilicon layer having a thickness of several hundred nanometers, followed by a patterning process to form a polysilicon fuse pattern 64 and a reserve capacitor electrode 65. Next, the part of the capacitor insulation film 63 not covered by the capacitor electrode 65 is removed by an etching process, and an SiO2 film 66 constituting the gate oxide film is formed so as to cover the fuse pattern 64 and the capacitor electrode 65. Further, a deposition process of a polysilicon layer is conducted on the SiO2 film 66 such that the polysilicon layer covers the SiO2 film 66 with a thickness of several ten nanometers. As a result of patterning of the polysilicon layer thus deposited, there are formed a gate electrode 67 and a polysilicon layer 68 covering the polysilicon fuse pattern 64. Further, an ion implantation process of an impurity element is conducted while using the gate electrode 67 as a mask, to form a diffusion region 69.
In the step of FIG. 3A, a CVD process is conducted further to form a PSG film 70 with a thickness of 1 xcexcm, followed by the step of forming a contact hole in correspondence to the source region 69. Further, an Al electrode 71 is formed so as to fill the contact hole formed previously, and a CVD process is conducted again to cover the entire structure by a PSG film 72 with a thickness of 1 xcexcm.
Next, in the step of FIG. 3B, a fuse window 73 is formed in the PSG films 72 and 70 in correspondence to the polysilicon fuse pattern 64 by a dry etching process conducted by using CHF3 as an etching gas. During this dry etching process, the polysilicon layer 68 functions as an etching stopper.
Next, in the step of FIG. 3C, the polysilicon layer 68 is selectively removed by a dry etching process using CHF3 as an etching gas, and a dry etching process using the CHF3 etching gas is conducted again to remove the SiO2 film 66 covering the polysilicon fuse pattern 64. After this, the polysilicon fuse pattern 64 to be disconnected is blown by supplying an electric current (see Japanese Laid-Open Patent Publication 58-161361).
Depending on the case, the SiO2 film 66 may be left on the polysilicon fuse pattern 64.
FIGS. 4A-4C show another conventional fabrication process of a polysilicon fuse pattern.
Referring to FIG. 4A, a Si substrate 81 is defined with a predetermined device region 82 and is covered with a first insulation film 83 such that the first insulation film 83 covers the entirety of the Si substrate 81. After the formation of the first insulation film 83, a contact hole is formed in correspondence to the device region 82 and a polysilicon layer is deposited on the entirety of the first insulation film 83 so as to include the contact hole thus formed. By pattering the polysilicon layer thus formed, a polysilicon electrode 84 and a polysilicon fuse pattern 85 are formed. Next, a second insulation film 86 is formed on the entirety of the insulation film 83 with a thickness of 1.0 xcexcm so as to cover the electrode 84 and the fuse pattern 85, followed by the step of forming a contact hole in the second insulation film 86 thus formed, and the contact hole thus formed is covered with a film of Pt. By applying a heat treatment to the Pt film thus deposited at the temperature of about 500xc2x0 C. a Pt silicide layer 87 is formed in correspondence to the foregoing opening. Next, a Ti film is deposited on the entire surface of the insulation film 86, followed by a pattering process to form a barrier metal film 88 of Ti in correspondence to the foregoing opening. Similarly, a Ti pattern is formed on the polysilicon fuse pattern 85 as a stopper layer 89. Next, the entire surface of the insulation film 86 is covered with Al, followed by a pattering process, to form an Al interconnection layer 90. Thereafter, a third insulation film 91 is deposited so as to cover the interconnection layer 90 with a thickness of 1.5 xcexcm.
Next, in the step of FIG. 4B, there is formed a contact part 92 in the insulation film 91 so as to expose the Al interconnection layer 90 in correspondence to the device region 82. Simultaneously, a fuse window 93 is formed in correspondence to the part where the foregoing stopper layer 89 remains. Thereby, the fuse window 93 exposes the stopper layer 89.
Next, in the step of FIG. 4C, the Ti stopper layer 89 is selectively removed by H2O2 in the fuse window 93, and the polysilicon fuse pattern 85 to be disconnected is blown by irradiating a laser beam through the fuse window 93 (see Japanese Laid-Open Patent Publication 3-50756).
Thus, in the conventional proposal of FIGS. 3A-3C or FIGS. 4A-4C achieves a uniform thickness in the insulation film covering the fuse patterns by using an etching stopper. Thereby, the fuse patterns are blown with reliability by applying thereto a laser beam of a predetermined intensity.
In the semiconductor fabrication process of FIGS. 1A-1C, there arises a problem, associated with the construction not using etching stopper film, in that the control of the RIE process is difficult when forming the window 51. Thereby, there is a tendency that the film thickness distribution of the protective film 49 influences the film thickness of the insulation film 44 remaining on the fuse patterns. When such a variation exists in the thickness of the insulation film 44. the desired reliable laser-blowing of the fuse patterns becomes difficult. Further, the tolerable power band of the laser beam for achieving the desired blowing the fuse patterns is narrowed.
In the process of FIGS. 2A-2D, on the other hand, the laser-blowing of the fuse pattern is certainly improved with regard to the reproducibility as a result of the use of the insulation film 53 in the fuse window. However, the process requires additional steps of forming the insulation film 53 and the etching of the same for forming the bonding opening. Thus, the fabrication process of the semiconductor device is substantially complicated.
In the process of FIGS. 3A-3D that uses the etching stopper film, the reproducibility of the laser-blowing of the fuse pattern is improved. On the other hand, the process requires a complex switching of the etching gases during the etching process of the etching stopper film 68. Associated with this, it is necessary to provide various different gases. Further, the process of forming the bonding opening has to be made separately.
In the process of FIGS. 4A-4C, it is noted that the bonding opening 92 is formed simultaneously. However, the process of forming the bonding opening 92 is a wet etching process not suitable for the fabrication of highly miniaturized semiconductor integrated circuits.
In the case of the process of FIGS. 4A-4C, in which no planarization film such as SOG is used, the insulation film 91 has a generally uniform thickness. On the other hand, in view of the fact that the process does not take into account the effect of distribution of the film thickness, there is no consideration made on what problem may arise when a planarization film, which is used in recent highly miniaturized semiconductor devices, is provided in the process of FIGS. 4A-4C. Even if a dry etching process is combined with this process, there is no substantial teaching derived therefrom about the selection or switching of the etching gases. Thus, it is not clear what advantageous features other than the reliability of laser blowing process may be obtained as a result of such a combination.
In the conventional laser blowing process of the polysilicon fuse patterns 64 or 85, it should be noted that polysilicon constituting the fuse patterns 64 or 85 may scatter and cause a deposition on the side wall of the fuse window. When this occurs, there is a substantial risk that the polysilicon fuse 34 or 55, which has once been blown by the laser beam irradiation, resumes an electrical connection. Alternatively, the scattered polysilicon fragments may cause a short circuit in the adjacent fuse patterns formed in the same fuse window.
FIG. 5 shows the schematical cross sectional view of the polysilicon fuse pattern 64 taken along a longitudinal direction of FIG. 3C.
Referring to FIG. 5, it can be seen that the conductive fragments 75 of polysilicon are deposited on the side wall of the SiO2 film 76 upon laser blowing of the fuse pattern 64, wherein the conductive fragments 75 cause a short-circuit between the polysilicon fuse pattern 64 and the polysilicon layer 68.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a semiconductor device having fuse patterns and a fuse window cooperating with the fuse patterns, the fuse patterns being selectively blow by a laser beam irradiation, such that the blowing of the fuse pattern is achieved with reliability and reproducibility and such that the semiconductor device has a construction suitable for efficient fabrication.
Another object of the present invention is to provide a fabrication process of a semiconductor device, said semiconductor device comprising a substrate, a fuse pattern formed on said substrate, an etching stopper layer formed over said fuse pattern so as to cover an area in which said fuse pattern is formed, an interlayer insulation film covering said etching stopper layer, a conductor pattern formed on said interlayer insulation film, a protective film formed on said interlayer insulation film so as to cover said conductor pattern, a bonding contact pad formed in said protective film so as to expose said conductor pattern, and a window formed in said protective film in correspondence to said fuse pattern so as to penetrate through said interlayer insulation film and said etching stopper layer, said method including the step of forming said window, said step of forming said window comprising the steps of:
forming a first opening through said protective film and said interlayer insulation film so as to expose said etching stopper layer; and
forming a second opening in continuation to said first opening by applying an etching process to said etching stopper layer through said first opening,
said step of forming said first opening being conducted concurrently with a step of forming said bonding contact pad.
According to the present invention, the fuse cover film, which covers the fuse patterns and exposed at the fuse window, has a uniform thickness as a result of the process that includes the steps of: covering the fuse patterns by the etching stopper layer; and forming the fuse window in the form of the first and second openings. This advantageous feature is obtained even in such a case in which the planarization film is interposed between the interlayer insulation film and the protective film with a varying thickness. Thereby, the blowing of the fuse patterns conducted by the laser beam through the fuse window is achieved reliably and with excellent reproducibility. Further, the fuse-to-fuse variation or chip-to-chip variation of the fuse blowing property is successfully eliminated. In the foregoing process of the present invention, it should be noted that the formation of the bonding opening and the formation of the first window are conducted simultaneously. Thereby, the number of fabrication steps of the semiconductor device is reduced and the semiconductor device is produced with an increased throughput.
Another object of the present invention is to provide a fabrication process of a semiconductor device, said semiconductor device comprising a substrate, a fuse pattern formed on said substrate, an etching stopper layer formed over said fuse pattern so as to cover an area in which said fuse pattern is formed, an interlayer insulation film covering said etching stopper layer, a conductor pattern formed on said interlayer insulation film, a protective film formed on said interlayer insulation film so as to cover said conductor pattern and a window formed in said protective film in correspondence to said fuse pattern so as to penetrate through said interlayer insulation film and said etching stopper layer, said method including the step of forming said window,
said step of forming said window comprising the steps of:
forming a first opening through said protective film and said interlayer insulation film so as to expose said etching stopper layer; and
forming a second opening in continuation to said first opening by applying an etching process to said etching stopper layer through said first opening,
wherein said step of forming said second opening is conducted such that the thickness of the fuse cover film decreases in said second opening.
According to the present invention, the thickness of the fuse cover film can be reduced as compared with the initial thickness thereof as a result of the etching process used in the step of forming the second opening. This means, in turn, that it is possible to maintain a sufficient thickness for the insulation film that is formed simultaneously with the foregoing fuse cover film. Thereby the stray capacitance pertinent to the insulation film is reduced. Because of the reduced thickness of the fuse cover film, the blowing of the fuse pattern can be achieved by using a low power laser beam.
Another object of the present invention is to provide a fabrication process of a semiconductor device, said semiconductor device comprising a substrate, a fuse pattern formed on said substrate, an etching stopper layer formed over said fuse pattern so as to cover an area in which said fuse pattern is formed, an interlayer insulation film covering said etching stopper layer, a conductor pattern formed on said interlayer insulation film, a protective film formed on said interlayer insulation film so as to cover said conductor pattern, a bonding contact pad formed in said protective film so as to expose said conductor pattern, and a window formed in said protective film in correspondence to said fuse pattern so as to penetrate through said interlayer insulation film and said etching stopper layer, said method including the step of forming said fuse window,
said step of forming said fuse window comprising the steps of:
forming said bonding contact pad and simultaneously a first opening through said protective film and said interlayer insulation film, such that said bonding contact pad exposes said conductor pattern;
covering said bonding contact pad by a resist pattern; and
forming a second opening in continuation to said first opening by applying an etching process to said etching stopper layer through said first opening.
According to the present invention, it becomes possible to form the second opening in continuation with the first opening in the semiconductor device, in which a multilayer interconnection structure is interposed between the etching stopper layer and the conductor pattern, even in such a case where the etching stopper is not exposed at the first opening in the instance in which the conductor pattern is exposed at the bonding contact pad, by protecting the conductor pattern exposed by the bonding contact pad by using a resist pattern. Thereby, the problem of excessive etching of the conductor pattern at the bonding opening is effectively avoided. As the exposed conductor pattern is thus protected by the resist pattern, it is possible to continue the etching process so as to expose the etching stopper layer at the second opening without problem. By etching the etching stopper layer further, there is formed the fuse window cooperating with the fuse patterns.
Another object of the present invention is to provide a semiconductor device, comprising a substrate, a fuse pattern formed on said substrate, a fuse cover film covering a region where said fuse pattern is formed, an etching stopper layer formed on said fuse cover film, an interlayer insulation film covering said etching stopper layer, and a window formed in said interlayer insulation film so as to penetrate through said etching stopper layer and expose the fuse cover film, said method including the step of forming said fuse window,
said interlayer insulation film having a first side wall defining said fuse window,
said etching stopper layer having a second side wall defining said fuse window,
said second side wall being formed at a position receded with respect to said first side wall.
According to the present invention, there is formed a space in the opening adjacent to the fuse pattern in correspondence to the receded second side wall. Thereby, any fuse fragments formed as a result of the laser blowing of the fuse pattern, are accommodated into the space and the problem of the short circuit caused by the scattered fuse fragments contacting with the etching stopper layer is successfully avoided.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.